Reference is made to U.S. Pat. Nos. 7,782,668 and 7,787,295 and U.S. patent application Ser. Nos. 12/264,029, 12/264,060, 12/264,076, 12/271,647, 12,271,666 and 12/271,680 all of which are hereby incorporated by reference.
The '668 patent discloses a new type of single-poly non-volatile memory device structure that can be operated either as an OTP (one time programmable) or as an MTP (multiple time programmable) memory cell. The device is programmed using hot electron injection. It also has a structure that is fully compatible with advanced CMOS logic process, and would require, at the worst case, very minimal additional steps to implement. Other unique aspects of the device are described in the '668 patent as well.
Recent developments have focused on incorporating Nonvolatile memory cell into pure CMOS logic or digital process, as well as into analog or high voltage process, all without incurring additional process complexities. The advantages of this approach can be implemented in logic integrated circuits, as well as analog integrated circuits and Power Management IC (PMIC). For example for PMICs, the beneficial applications of incorporating NVM cell into integrated circuits include reference trimming and calibration code storage to name a few.
One traditional approach to implement a low cost nonvolatile memory cell has been to use a basic logic or low voltage (LV) transistor structure and associated process steps. An example of this is shown in U.S. Pat. No. 7,852,672 incorporated by reference herein. As such, the nonvolatile memory structures will feature oxide thicknesses that are predetermined by what is already available in structures used in the LV/logic transistors. Typically the thickest oxide that is available for use within an embedded NVM cell therefore is from the oxide of the I/O transistors in the logic process. Such oxide has a maximum thickness that is typically in the range of 65 to 70 Angstroms for 3.3V I/O voltage level, and is optimized for a performance of logic gates. While this oxide thickness is thin enough to allow efficient channel hot electron programming and channel hot hole erasing, and is suitable for a majority of embedded storage functions, it would be desirable in some applications for the oxide thickness to be larger so as to meet certain types of applications which may require more stringent data retention and/or extended endurance cycling requirements. Thus, Applicant has determined it would be desirable to be able to implement a NVM cell in the analog or PMIC process that can have a more robust data retention characteristics through a thicker gate oxide.